The present invention relates to a simultaneous bidirectional transmission circuit for simultaneously transmitting and receiving signals by using a single transmission line. In particular, the present invention relates to a simultaneous bidirectional transmission circuit suitable for transmitting and receiving data between LSI (large-scale integrated circuit) chips even when the power supply voltage of LSIs is made low.
The simultaneous bidirectional transmission circuit has an input/output circuit at each of ends of a single transmission line, and transmits and receives signals simultaneously via the transmission line. As compared with a typical conventional transmission circuit using separate transmission lines respectively for the transmitting operation and the receiving operation, the number of lines is reduced to half. Therefore, the simultaneous bidirectional transmission circuit is especially useful, for example, in computers which transmit and receive several tens or more data. Typically in the computer application, a plurality of input/output circuits are contained in an LSI chip included in a computer. Between a pair of input/output circuits of LSI chips, a single transmission line is connected. In the case of a plurality of input/output circuits, a plurality of data are transmitted and received via a plurality of transmission lines. In some cases, the number of input/output circuits contained in a single LSI chip is one hundred or more.
In a conventional driver for sending a signal to a transmission line, the output resistance of a driver seen from a connection point of the driver with the transmission line should coincide with the impedance of the transmission line. The necessity of this impedance matching is described in the U.S. Pat. No. 4,719,369. In a driver disclosed in the U.S. Pat. No. 4,719,369, MOS transistors having different internal resistance values obtained by changing gate widths are connected in parallel. By selectively providing those MOS transistors with gate inputs, the output resistance of the driver is controlled so as to coincide with the characteristic impedance. Thus the impedance matching is accomplished.
On the other hand, a simultaneous bidirectional transmission circuit is disclosed in U.S. Pat. No. 5,514,983. A signal existing at the connection point of the simultaneous bidirectional transmission circuit with the input/output circuit contains a mixture of an output signal of the input/output circuit and a received signal which is sent from the other party and which should be received. In order to remove the output signal and extract the received signal from the mixed signal, a differential receiver is provided. By controlling the gate voltage of a reference circuit for outputting a part of the output signal to the differential receiver and the gate voltage of the final stage of the driver in an analog way, the output resistance is provided with a predetermined value.
As the gate voltage of nMOS transistors included in a transmission circuit and nMOS transistors included in the reference circuit described in the aforementioned U.S. Pat. No. 5,514,983, Vc1 outputted from a differential amplifier is supplied. Considering that the power supply voltage of current LSIs is typically 3.3 V, the Vc1 does not exceed 3.3 V, which is the power supply voltage VDD1 of the differential amplifier. Actually, since it is necessary to assure the control range of Vc1, the minimum value of Vc1 becomes approximately 2.5 V. Furthermore, for keeping the output resistance of each of nMOS transistors at a constant value, it is necessary to make the transistors operate in a triode region as described in the U.S. Pat. No. 5,514,983. It is thus necessary to set the power supply voltage VDD2 to be supplied to the drain terminal of each of these nMOS transistors to a voltage of (Vc1-Vth) or less, where Vth is the threshold voltage of an nMOS transistor activated in the source follower operation and Vth is typically at least 1 V. Furthermore, taking the dispersion of the power supply voltage into consideration, the practical value of the VDD2 is approximately 0.8 V. In this case, the (+) input of the differential amplifier based upon the ternary logic has a value of 0.8 V (=VDD2), 0.4 V (=VDD2/2), or 0 V, and the (-) input of the differential amplifier functioning as the reference signal has a value of 0.6 V (=3VDD2/4) or 0.2 V (=VDD2/4). The input amplitude between the (+) input and the (-) input of the differential amplifier becomes .+-.200 mV. It is significantly smaller than .+-.400 mV which is the operation amplitude of typical differential amplifiers. Thus, an amplitude large enough to withstand noise cannot be assured. When the method of controlling the output resistance by using the gate voltage of nMOS transistors as described in the U.S. Pat. No. 5,514,983 is employed, therefore, it is difficult to assure the input amplitude of the differential amplifier for the power supply voltage under the present situation, i.e., 3.3 V, or a lower power supply voltage value in the future. Furthermore, since the Vc1 is generated by an analog feedback loop, problems of noise and oscillation are also posed.